A VHDL-described 8-issue VLIW soft-processor for fast packet processing on FPGA 1 0 0 Packet Manipulator Processor Marco Spaziani Brunella Created: 08/09/2017
An hardware implementation of a stateful dataplane based on XFSM. 1 0 0 Open Packet Processor Marco Spaziani Brunella Created: 08/11/2017
